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PCI Express pumps up performance

In the past decade, PCI has served as the dominant I/O architecture for PCs and servers, carrying data generated by microprocessors, network adapters, graphics cards and other subsystems to which it is connected. However, as the speed and capabilities of computing components increase, PCI’s bandwidth limitations and the inefficiencies of its parallel architecture increasingly have become bottlenecks to system performance.

PCI is a unidirectional parallel bus architecture in which multiple adapters must contend for available bus bandwidth. Although performance of the PCI interface has been improved over the years, problems with signal skew (when bits of data arrive at their destination too late), signal routing and the inability to lower the voltage or increase the frequency, strongly indicate that the architecture is running out of steam. Additional attempts to improve its performance would be costly and impractical. In response, a group of vendors, including some of the largest and most successful system developers in the industry, unveiled an I/O architecture dubbed PCI Express (initially called Third Generation I/O, or 3GIO).

PCI Express is a point-to-point switching architecture that creates high-speed, bidirectional links between a CPU and system I/O (the switch is connected to the CPU by a host bridge). Each of these links can encompass one or more “lanes”comprising four wires——two for transmitting data and two for receiving data. The design of these lanes enables the use of lower voltages (resulting in lower power usage), reduces electromagnetic emissions, eliminates signal skew, lowers costs through simpler design and generally improves performance.

In its initial implementation, PCI Express can yield transfer speeds of 2.5G bit/sec in each direction, on each lane. By contrast, the version of the PCI architecture that is most common today, PCI-X 1.0, offers 1G bit/sec in throughput. PCI Express cards are available in four- or eight-lane configurations (called x4 and x8). An x4 PCI Express card can provide as much as 20G bit/sec in throughput, while an x8 PCI Express card can offer up to 40G bit/sec in throughput.

Earlier attempts to create a new PCI architecture failed in part because they required so many changes to the system and application software. Drivers, utilities and management applications all would have to be rewritten. PCI Express developers removed the dependency on new operating system support, letting PCI-compatible drivers and applications run unchanged on PCI Express hardware.

A bus for the future

Developers are working on increasing the scalability of PCI Express. While current server and desktop systems support PCI Express adapters and graphics cards with up to eight lanes (x8), the architecture will support as many as 32 lanes (x32) in the future.

The first Fibre Channel host bus adapters were designed to support four lanes instead of eight lanes, in part because server developers had designed their systems with four-lane slots. As even more bandwidth is required, implementing an eight-lane design potentially could double the performance, provided there were no other bottlenecks in the system.

This scalability, along with the expected doubling of the speed of each lane to 5G bit/sec, should keep PCI Express a viable solution for designers for the foreseeable future.

PCI Express is a significant improvement over PCI and is well on its way to becoming the new standard for PCs, servers and more. Not only can it lower costs and improve reliability, but it also significantly can improve performance. Applications such as music and videostreaming, video on demand, VoIP and data storage will benefit from these improvements.

PCI Express总线提升性能

在过去十年间，PCI总线一直是PC机和服务器上的主流I/O架构，它负责将微处理器、网卡、图形卡和其他子系统生成的数据送到与它相连的部件。然而，随着计算部件的速度和能力的提高，PCI并行架构的带宽局限性和低效率越来越成为系统性能的瓶颈。

PCI是一个单向的并行总线架构，其中多个适配器必须争夺可用的总线带宽。虽然PCI接口的性能几年来不断得到改进，但信号偏离(数据位到达目的地太晚)、信号路由、以及电压无法降低或频率更高时就不能正常工作等问题，无不表明该架构走到了尽头。改进其性能的设想代价很高，也不实际。针对此问题，一些厂商(包括最大的和最成功的系统开发商)公布了一个叫PCI Express(最初叫第三代I/O，缩写为3GIO)的I/O架构。

PCI Express是一个点对点的交换架构，在CPU和系统I/O之间建立高速的双向链路(交换机由主桥接到CPU)。每一个链路可以包含一个或多个由四条电线组成的“通道”，其中两条线发送数据，两条线接收数据。这些通道的设计能允许在低压下使用(这样功率消耗较少)、降低电磁辐射、消除信号偏离、以及简化设计带来的成本降低，总的来说改进了性能。

在其最初的实现中，PCI Express就能保证在每个通道上双向的传输速度达到2.5G位/秒。而目前最常见的PCI架构版本——PCI-X 1.0提供的吞吐量为1G 位/秒。目前能得到的PCI Express卡为4通道或8通道的配置(叫x4和x8)。x4 PCI Express卡能提供的吞吐量达到20G 位/秒，而x8 PCI Express卡能提供的吞吐量则高达40G 位/秒。

早期创建新的PCI架构的设想之所以失败了，是因为要求系统和应用软件做太多的修改，驱动程序、例行程序和管理应用程序全都必须重写。PCI Express开发者消除了对新操作系统支持的依赖，让与PCI兼容的驱动程序和应用程序无需更改就能在PCI Express硬件上运行。

未来的总线

目前，开发者正在研究如何提高PCI Express的可扩展性。现在的服务器和台式系统支持多达8通道(x8)的PCI Express卡和图形卡，而将来该架构能支持多达32通道(x32)。

第一个光纤通道的主总线适配器设计成支持4通道，不是8通道，部分原因是由于服务器开发商已经将其系统设计了4通道插槽。当需要更多带宽时，实现8通道的设计能使性能翻一番，只要系统中没有其他的瓶颈。

此可扩展性加上每个通道的速度有望加倍，达到5G位/秒，应该可以使PCI Express在可预计的未来成为设计师可用的选择方案。

PCI Express相对PCI是一次重大的改进，它正在沿着成为PC机、服务器以及更多设备新标准的道路前进。它不仅降低了成本、提高可靠性，而且还能显著地改善性能。音乐和视频流、视频点播、网络电话和数据存储等应用程序也将从这些改进中受益。